This invention relates in general to the field of integrated electronic systems and more particularly to the architecture and formation of a vertical bipolar transistor constructed using adjunct CMOS processes.
The construction of field effect devices in CMOS technologies involves the use of sequential implant processes to form conductive and semiconductive regions within the outer surface of a semiconductor substrate. These implant processes are optimized to enable the field effect devices to function in complimentary fashion. P-channel devices and n-channel devices are formed on the same substrate using photolithographic processes to cover certain of the devices while implant processes are performed on the remaining devices.
State of the art bipolar transistors require different implant and photolithographic masking processes. Many integrated architectures require or may be optimized if the integrated system can utilize both field effect and bipolar devices on the same integrated substrate. Unfortunately, the use of implant processes to form field effect devices and then subsequent implant processes to form bipolar devices greatly increases the cost and complexity of the formation of the device. As such, designers have attempted to use the same implant processes for the field effect devices to create various bipolar structures within the integrated system. These techniques have been somewhat successful but they have been limited principally because bipolar devices require two junctions. In this regard, many of the bipolar devices that have been integrated with field effect devices have used the substrate itself as one of the active regions of the bipolar device. While this technique can create a functioning bipolar transistor, this technique is limited because the substrate voltage is automatically applied to one terminal of the bipolar device. This greatly limits the operational parameters of such a bipolar device and can reduce the effectiveness of the device in the integrated architecture.
Accordingly, a need has arisen for a new architecture and techniques for forming a bipolar transistor using the operations used to form CMOS devices in an integrated semiconductor system.
In accordance with the teachings of the present invention, integrated device architectures are provided herein that include vertical bipolar transistors formed using implant steps associated with the formation of adjunct CMOS devices. These techniques substantially reduce or eliminate problems associated with prior device architectures and formation techniques.
In accordance with one embodiment of the present invention, a bipolar device is formed in parallel with an nMOS field effect device and a pMOS field effect device. An n-type source drain implant is used to form the source and drain for the nMOS field effect device and the emitter of a vertical bipolar device. A channel stop implant is used to dope the channels of the field effect devices and is also used to form the base region of the vertical bipolar device. A p-type implant process is used to form the source drain regions of pMOS field effect devices and is also used to form a contact region for the base region of the vertical bipolar device. An n-type implant is used to form an n-type well associated with pMOS field effect devices and is also used to form a collector region disposed inwardly from the base region of the vertical bipolar device. The n-type source drain implant is used to form the emitter region and the source and drain region of nMOS field effect devices. This implant is also used to form a contact region for the collector region of the vertical bipolar device.
An important technical advantage of the present invention inheres in the fact that implant processes which are used to form field effect devices on an integrated substrate can also be used to form vertical bipolar devices on the same substrate. In this manner, bipolar transistors can be used with both pMOS and nMOS field effect devices to create complex BiCMOS circuitry without incurring the complexity and costs associated with conventional techniques for forming these structures.
An important technical advantage of the present invention inheres in the fact that the vertical bipolar device constructed according to one embodiment of the present invention is isolated from substrate of the device by a p-n junction. As such, the collector of the vertical bipolar device can be contacted through the outer substrate surface and can be connected to whatever voltage is desired for the operation of the device. This capability greatly enhances the flexibility of the operation of the device within an integrated circuit.